1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a delay test circuit, and a method for testing the semiconductor integrated circuit. More specifically, the present invention relates to a technique for facilitating a test of a semiconductor integrated circuit using a scan path.
2. Description of the Related Art
One of the most widely used techniques for facilitating a test of a semiconductor integrated circuit is a scan design technique for incorporating scan paths into the semiconductor integrated circuit. Specifically, the flip-flops of a core logic are connected in series to form the scan path, and a selector is additionally provided for a data input of each of flip-flops. The flip-flops are often referred to as “scan flip-flops”. This scan path functions as a very large scale of shift register. At the time of testing the core logic, a data is directly written into or read from the scan flip-flops using the scan path so as to test operations of the core logic.
One of the important points of the test is to use the scan path to realize an at-speed delay test, in other words, is to use the scan path to realize a delay test at a same operating rate as a normal operating rate when the semiconductor integrated circuit. This is because a fault that inappropriate delay is caused in the semiconductor integrated circuit may be present in the circuit despite a logically correct circuit configuration. Such a fault needs to be detected by so-called at-speed delay test.
It is a restriction on an operating rate of an LSI tester that makes it difficult to carry out the at-speed delay test. For the reason of recent improvement in the operating rate of the semiconductor integrated circuit, the LSI tester needs to have a high operating rate for the at-speed delay test. However, the use of the LSI tester having the high operating rate pushes up a test cost and is disadvantageous against a manufacturing cost of the semiconductor integrated circuit.
A technique is known in which the at-speed delay test is used with a tester of relatively low operating rate by incorporating a PLL circuit into a target semiconductor integrated circuit to generate a clock signal. By incorporating the PLL circuit into the semiconductor integrated circuit, it is unnecessary to supply a high frequency clock signal from the tester to the target semiconductor integrated circuit. Thus, it becomes possible to carry out the at-speed delay test by using the tester having a relatively low operating rate.
For instance, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-P2002-196046A), which includes a PLL circuit configured to continuously output a desired number of clock pulses in response to an external control signal. More specifically, the PLL circuit includes a PLL oscillator to generate a clock signal having a frequency corresponding to a same operating rate as a normal operating rate of the semiconductor integrated circuit, and a counter to count up in synchronization with the clock signal. When a counter value of the counter is greater than l and smaller than m (where l and m are natural numbers that satisfy l<m), the PLL circuit outputs the clock signal without masking it. Otherwise, the PLL circuit outputs a masked clock signal. By employing such a configuration, (m−l−1) continuous clock pulses can be taken out from the clock signal generated by the PLL oscillator, as shown in FIG. 1. It should be noted that “output of the n continuous clock pulses” means that clock pulses are continuously outputted over n clock cycles. When the at-speed delay test is carried out, these continuous clock pulses are supplied to an internal circuit.
A typical procedure of the at-speed delay test to the semiconductor integrated circuit will now be described with reference to an instance in which a target semiconductor integrated circuit is configured as shown in FIG. 2. The semiconductor integrated circuit shown in FIG. 2 includes scan flip-flops 101, 103, 105, and 107, and combinational circuits 102, 104, and 106. The scan flip-flops 101, 103, 105, and 107 are connected in series to constitute a scan path 108. Also, the combinational circuit 102 is connected with the scan flip-flops 101 and 103, the combinational circuit 104 is connected with the scan flip-flops 103 and 105, and the combinational circuit 106 is connected with the scan flip-flops 105 and 107. For simplification of the description, it is assumed that each of the combinational circuits 102, 104, and 106 is a single cycle path, that is, the combinational circuit is designed to transmit data in a single clock cycle. Most of the combinational circuits integrated into the semiconductor integrated circuit are single cycle paths. The procedure for the delay test carried out to the combinational circuit 106 in the semiconductor integrated circuit shown in FIG. 2 will be described.
First, an initialization pattern to be supplied to the combinational circuit 106 is set to the scan flip-flops 105 by using the scan path 108. Thus, each node of the combinational circuit 106 is initialized to a desired state. At the same time, a “test pattern generation pattern” is set to the scan flip-flops 103 such that an output of the combinational circuit 104 is set to values of a desired test pattern and then supplied to the combinational circuit 106 through the scan flip-flops 105.
Subsequently, a first clock pulse is supplied from a PLL circuit included in the semiconductor integrated circuit to the scan flip-flops 105 as well as other scan flip-flops. This first clock pulse is often referred to as a “launch clock”. In response to this launch clock, the scan flip-flops 105 latch a test pattern from the output of the combinational circuit 104 and supply the latched test pattern to the combinational circuit 106. By supplying the test pattern to the combinational circuit 106, a desired state transition occurs in a fault assumed point, e.g., a wiring or a terminal of a primitive, in the combinational circuit 106. For instance, a logic “1” is set to the fault assumed point in the combinational circuit 106 based on the initialization pattern, and the fault assumed point is then changed to a logic “0” based on the test pattern. Alternatively, the logic “0” is set to the fault assumed point thereof based on the initialization pattern and the logic “1” is then set thereto based on the test pattern.
Next, a second clock pulse is supplied from the PLL circuit to the scan flip-flops 107 as well as other scan flip-flops and the output of the combinational circuit 106 is latched by the scan flip-flops 107. This second clock pulse is often referred to as a “capture clock”. Data latched by the scan flip-flops 107 in response to the capture clock is transferred to the LSI tester through the scan path 108. Based on the transferred data, the LSI tester determines whether or not a transition delay fault is present in the combinational circuit 106. If the data latched by the scan flip-flops 107 coincides with an expected value pattern prepared in advance, the LSI tester determines that the state of the fault assumed point in the combinational circuit 106 is changed as designed. If the data latched by the scan flip-flops 107 does not coincide with the expected value pattern, the LSI tester determines that a transition delay fault is present in the combinational circuit 106.
The initialization pattern, the test pattern generation pattern, and the expected value pattern are normally generated by an automatic test pattern generation (ATPG) tool. To generate these patterns for the delay test to the combinational circuit 106, the ATPG tool needs to regard the combinational circuit 104, the scan flip-flops 105, and the combinational circuit 106 as a sequential circuit, and to analyze the operation of the sequential circuit over two clock cycles.
In addition, a semiconductor integrated circuit is disclosed in “DFT Timing Design Methodology for At-Speed BIST”, by Yasuo Sato et al. (Proceedings of ASP-DAC 2003, pp. 763-768, IEEE) as a second conventional example. In this conventional example, the semiconductor integrated circuit includes a PLL circuit to supply clock pulses used in an at-speed delay test to each of flip-flops belonging to different clock domains. The “clock domain” means a set of circuits to which a clock signal is supplied from one clock tree. The second conventional example points out that a difference in delay between the clock trees is an obstacle to the at-speed delay test to an inter-domain path, which is a path for transmitting a signal from a flip-flop belonging to one clock domain to a flip-flop belonging to another clock domain. To carry out the at-speed delay test to the inter-domain path, an appropriate number of delay gates are incorporated in the semiconductor integrated circuit in a range from the PLL circuit to inputs of the respective clock trees. By incorporating the delay gates, the difference in delay between the clock trees is compensated to facilitate execution of the at-speed delay test to the inter-domain path.
However, the technique disclosed in the first conventional example is disadvantageous in testability of a multi-cycle path. The multi-cycle path means a combinational circuit to which data is transferred over a plurality of clock cycles. Many combinational circuits are designed to serve as the single cycle path. However, depending on specification of the semiconductor integrated circuit, it is often desirable to use the multi-cycle path. In the semiconductor integrated circuit with the PLL circuit which can generate only continuous clock pulses, as disclosed in the first conventional example, the presence of this multi-cycle path is quite inconvenient for the at-speed delay test using the ATPG tool.
More specifically, the clock periods necessary for analysis by the ATPG tool increases as the number of clock cycles necessary for data to be transmitted to the combinational circuit increases. Generally, in case of the multi-cycle path in which the data is transmitted to the combinational circuits in N clock periods, it is necessary to analyze an operation of the sequential circuit over (N+1) clock periods.
In addition, a scale of the sequential circuit to be analyzed is made large as the number of clock periods necessary for the data transmission to the combinational circuit increases.
The above facts will be described specifically by using the semiconductor integrated circuit shown in FIG. 2. If the combinational circuit 106 is the multi-cycle path to which data is transmitted in two clock periods, a circuit constituted by the combinational circuits 102, 104, and 106, and the scan flip-flops 103 and 105 is assumed as the sequential circuit. It is necessary to analyze the operation of the sequential circuit for three clock periods. The reason is as follows. If the above-stated PLL circuit is used to generate only continuous clock pulses, another clock pulse is supplied to the scan flip-flop 105 between the launch clock for allowing the scan flip-flops 105 to latch the test pattern and the capture clock for allowing the scan flip-flops 107 to latch the output from the combinational circuit 106. It is required to continuously supply such a pattern that a desired state transition occurs in the fault assumed point in the combinational circuit 106 over three clock periods. For this purpose, it is necessary to analyze the operation of the sequential circuit over three clock periods and also determine the patterns to be set to the scan flip-flops 101, 103, and 105. It should be noted that it is sufficient to analyze the operation of the sequential circuit constituted by the combinational circuits 104 and 106 and the scan flip-flop 105 over two clock periods if the combinational circuit 106 is the single clock path.
As could be understood, the use of the multi-cycle path disadvantageously increases a data processing amount necessary for the ATPG tool to generate the test patterns, and necessitates a large capacity of memory to store internal states of the semiconductor integrated circuit, such as the values of scan flip-flops in each clock period. For the semiconductor integrated circuit as large as over ten million gates in scale, increases in the necessary data processing amount and memory capacity are too serious to be accepted economically. Therefore, when the semiconductor integrated circuit includes the PLL circuit that can generate only continuous clock pulses, it is eventually impossible to carry out the at-speed delay test to the multi-cycle path.
Meanwhile, in the second conventional example, an unpractical design restriction is sometimes imposed on the semiconductor integrated circuit to adjust delays of the clock trees. The difference in delay between one clock tree and another clock tree is sometimes as great as ten nanoseconds. In the recent high-speed operation semiconductor integrated circuit, the delay time of one gate is about 100 picoseconds. Therefore, in order to compensate the above delay difference, it would be necessary to provide impractically large number of delay gates between the PLL circuit and the input of the clock tree for adjusting the delays of the clock trees by the delay gates. This indicates that it is impractical to carry out the at-speed delay test to the inter-domain path by adjusting the delay difference between the clock trees by using the delay gates.
As could be understood from the above, no practical techniques for carrying out the at-speed delay test to the multi-cycle path or the inter-domain path are present.